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See Technical Specifications

CD40103BPW

CMOS 8-Stage Presettable 8-Bit Binary Synchronous Down Counter

Manufacturer:

Texas Instruments
Mfr.Part #:

CD40103BPW
Datasheet:

CD40103BPW Datasheet (PDF)
Mounting Style:

SMD/SMT
Counter Type:

Binary
Logic Family:

CD4000
Number of Bits:

1 bit

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

CD40103BPW General Description

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period.

When the SYNCHRONOUS PRESET-ENABLE (SPE)\ input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input. When the ASYNCHRONOUS PRESET-ENABLE (APE)\ input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE\, CI/CE\, or CLOCK inputs. JAM inputs JO-J7 represent two 4-bit BCD words for the CD40102B and a single 8-bit binary word for the CD40103B. When the CLEAR (CLR)\ input is low, the counter is asynchronously cleared to its maximum count (99₁₀ for the CD40102B and 255₁₀ for the CD40103B) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except CI/CE\ are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.

This causes the CO/ZD\ output to go low to enable the clock on each succeeding clock pulse.

The CD40102B and CD40103B may be cascaded using the CI/CE\ input and CO/ZD\ output, in either a synchronous or ripple mode as shown in Figs. 21 and 22.

The CD40102B and CD40103B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40103B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

Key Features

Synchronous or asynchronous preset
Medium-speed operation: f_CL = 3.6 MHz (typ.) @ V_DD = 10V
Cascadable
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
1 V at V_DD = 5 V
2 V at V_DD = 10 V
2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Divide-by-"N" counters
- Programmable timers
- Interrupt timers
- Cycle/program counter

CD40102B - 2-Decade BCD Type
CD40103B - 8-Bit Binary Type

Specifications

Product Category	Counter ICs	Mounting Style	SMD/SMT
Counter Type	Binary	Logic Family	CD4000
Number of Bits	1 bit	Counting Sequence	Down
Operating Supply Voltage	3 V to 18 V	Minimum Operating Temperature	- 55 C
Maximum Operating Temperature	+ 125 C	Series	CD40103B
Function	Counter	Operating Temperature Range	- 55 C to + 125 C
Output Current	+/- 1.5 mA	Product Type	Counter ICs
Factory Pack Quantity	90	Subcategory	Counter ICs
Unit Weight	0.002183 oz