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See Technical Specifications

EP610PI-30

CPLD Classic Family 300 Gates 16 Macro Cells 41.7MHz 5V 24-Pin PDIP

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Tel: +852 95804164

* Programmable Logic Device (PLD) IC Macrocells

High-performance, 16-macrocell Classic EPLD
t
PD
as fast as 10 ns
Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation
Available in the following packages (see
Figure 7

feature-family-name	Classic	feature-device-logic-cells
feature-program-memory-type	EPROM	feature-memory-size-kbit
feature-ram-bits-kbit		feature-number-of-logic-blocks-elements
feature-number-of-macro-cells	16	feature-number-of-product-terms-per-macro	8
feature-process-technology		feature-device-system-gates	300
feature-number-of-user-i-os	22	feature-number-of-flip-flops
feature-programmability	Yes	feature-programmable-type
feature-maximum-internal-frequency-mhz	33.3(Min)	feature-speed-grade	30
feature-in-system-programmability	No	feature-minimum-operating-supply-voltage-v	4.5
feature-maximum-operating-supply-voltage-v	5.5	feature-packaging
feature-rad-hard		feature-pin-count	24
feature-supplier-package	PDIP	feature-standard-package-name1	DIP
feature-cecc-qualified	No	feature-esd-protection
feature-military	No	feature-aec-qualified	No
feature-aec-qualified-number		feature-auto-motive	No
feature-p-pap	No	feature-eccn-code	EAR99
feature-svhc		feature-svhc-exceeds-threshold