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See Technical Specifications

SN65LV1023AMDBREP

Enhanced product 10:1 LVDS SerDes transmitter 100 to 660-Mbps

Manufacturer:

Texas Instruments, Inc
Mfr.Part #:

SN65LV1023AMDBREP
Datasheet:

SN65LV1023AMDBREP Datasheet (PDF)
Protocols:

HiRel Enhanced Product
Rating:

HiRel Enhanced Product
Operating temperature range (°C):

-55 to 125
feature-function:

Serializer
EDA/CAD Models:

Request Free CAD Models for SN65LV1023AMDBREP

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SN65LV1023AMDBREP General Description

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C.

Key Features

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Extended Temperature Performance of -55°C to 125°C
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree⁽¹⁾
100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System Clock
Pin-Compatible Superset of DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout

⁽¹⁾ Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Specifications

Protocols	HiRel Enhanced Product	Rating	HiRel Enhanced Product
Operating temperature range (°C)	-55 to 125	feature-function	Serializer
feature-number-of-drivers	1	feature-number-of-receivers	10
feature-number-of-elements-per-chip	1	feature-transmission-data-rate-mbps	660
feature-maximum-propagation-delay-time-ns		feature-input-signal-type	LVTTL\|LVCMOS
feature-differential-input-low-threshold-voltage-v	-0.05(Min)	feature-differential-input-high-threshold-voltage-v	0.05(Max)
feature-maximum-differential-output-voltage-v	0.45(Typ)	feature-maximum-input-current-ua	200
feature-supplier-temperature-grade	Extended	feature-packaging	Tape and Reel
feature-rad-hard		feature-pin-count	28
feature-cecc-qualified	No	feature-esd-protection
feature-escc-qualified		feature-military	No
feature-aec-qualified	No	feature-aec-qualified-number
feature-auto-motive	No	feature-p-pap	No
feature-eccn-code	EAR99	feature-svhc	Yes
feature-svhc-exceeds-threshold	No