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XC2V500-5FG256I +BOM

FPGA - Field Programmable Gate Array

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XC2V500-5FG256I General Description

Virtex®-II Field Programmable Gate Array (FPGA) IC 172 589824 256-BGA

Specifications

Pbfree Code No Part Life Cycle Code Obsolete
Pin Count 256 Reach Compliance Code not_compliant
ECCN Code EAR99 HTS Code 8542.39.00.01
Clock Frequency-Max 750 MHz Combinatorial Delay of a CLB-Max 0.39 ns
JESD-30 Code S-PBGA-B256 JESD-609 Code e0
Length 17 mm Moisture Sensitivity Level 3
Number of CLBs 768 Number of Equivalent Gates 500000
Number of Inputs 172 Number of Logic Cells 6912
Number of Outputs 172 Number of Terminals 256
Organization 768 CLBS, 500000 GATES Peak Reflow Temperature (Cel) 225
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY Qualification Status Not Qualified
Seated Height-Max 2 mm Supply Voltage-Max 1.575 V
Supply Voltage-Min 1.425 V Supply Voltage-Nom 1.5 V
Surface Mount YES Technology CMOS
Terminal Finish Tin/Lead (Sn63Pb37) Terminal Form BALL
Terminal Pitch 1 mm Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 30 Width 17 mm

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