This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

49FCT3805APYGI +BOM

Clock distribution device for dividing a single clock signal into five separate outputs

Manufacturer:

RENESAS
Mfr.Part #:

49FCT3805APYGI
Datasheet:

49FCT3805APYGI Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

20
Reach Compliance Code:

compliant
EDA/CAD Models:

Request Free CAD Models for 49FCT3805APYGI

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

49FCT3805APYGI General Description

Additionally, the FCT3805 offers the flexibility to accommodate two different input frequencies on bank A and B, as detailed in application note AN-236. This capability expands the versatility and applicability of the device, making it a versatile solution for a variety of clock distribution requirements in modern electronic systems

Key Features

3.3V operation

High-speed clock operation: 85 MHz (5V)

Functionally and pinout compatible with the IDT 72124

Low skew: 250ps

Low voltage operation: Vcc = 3.3V±0.3V

TTL-compatible inputs and outputs

Available in a 48-pin SSOP package

Specifications

Source Content uid	49FCT3805APYGI	Pbfree Code	Yes
Part Life Cycle Code	Active	Pin Count	20
Reach Compliance Code	compliant	ECCN Code	NLR
HTS Code	8542390001	Family	FCT
Input Conditioning	SCHMITT TRIGGER	JESD-30 Code	R-PDSO-G20
Logic IC Type	LOW SKEW CLOCK DRIVER	Moisture Sensitivity Level	1
Number of Functions	2	Number of Inverted Outputs
Number of Terminals	20	Number of True Outputs	5
Output Characteristics	3-STATE	Packing Method	TUBE
Peak Reflow Temperature (Cel)	260	Surface Mount	YES
Technology	CMOS	Terminal Finish	MATTE TIN
Terminal Form	GULL WING	Terminal Position	DUAL
Time@Peak Reflow Temperature-Max (s)	30