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See Technical Specifications

A3P1000-PQ208 +BOM

231MHz 130nm Technology

Manufacturer:

Microchip Technology
Mfr.Part #:

A3P1000-PQ208
Datasheet:

A3P1000-PQ208 Datasheet (PDF)
Series:

ProASIC3
Programmabe:

Not Verified
Total RAM Bits:

147456
Number Of I/O:

154
EDA/CAD Models:

Request Free CAD Models for A3P1000-PQ208

A3P1000-PQ208 General Description

The A3P1000-PQ208 FPGA by Microsemi is a cutting-edge solution for digital signal processing, image processing, and communication protocols. With its 100,000 logic elements and 2880 kilobits of memory, this FPGA offers high logic density and memory capacity for complex applications. The device's plastic quad flat pack (PQ208) package provides ease of soldering and handling during assembly, and its 1.2V operating voltage makes it energy-efficient for battery-operated applications. Additionally, the FPGA supports a wide range of functions and can be easily programmed using Microsemi's Libero SoC software, making it a versatile and user-friendly choice for FPGA design and implementation

Key Features

High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
FlashLock® to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os‡
Programmable Output Slew Rate† and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Specifications

Series	ProASIC3	Programmabe	Not Verified
Total RAM Bits	147456	Number of I/O	154
Number of Gates	1000000	Voltage - Supply	1.425V ~ 1.575V
Mounting Type	Surface Mount	Operating Temperature	0°C ~ 85°C (TJ)
Base Product Number	A3P1000