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See Technical Specifications

A3P250-VQG100T +BOM

Packaged in a 100-pin VQFP tray for easy integration into electronic systems

Manufacturer:

MICROCHIP TECHNOLOGY INC
Mfr.Part #:

A3P250-VQG100T
Datasheet:

A3P250-VQG100T Datasheet (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Factory Lead Time:

52 Weeks

A3P250-VQG100T General Description

Featuring a high-performance ARM Cortex-M3 processor, secure boot capabilities, and AES encryption, the A3P250-VQG100T FPGA prioritizes security and efficiency in its design. These advanced features ensure that sensitive data and operations are protected, making it an attractive option for applications where security is paramount. With its comprehensive feature set and powerful processing capabilities, the A3P250-VQG100T is poised to deliver exceptional performance in demanding applications

Key Features

High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
FlashLock® to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os‡
Programmable Output Slew Rate† and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Specifications

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Factory Lead Time	52 Weeks
Clock Frequency-Max	350 MHz	JESD-30 Code	S-PQFP-G100
JESD-609 Code	e3	Length	14 mm
Moisture Sensitivity Level	3	Number of CLBs	6144
Number of Equivalent Gates	250000	Number of Inputs	68
Number of Logic Cells	6144	Number of Outputs	68
Number of Terminals	100	Operating Temperature-Max	125 °C
Operating Temperature-Min	-40 °C	Organization	6144 CLBS, 250000 GATES
Peak Reflow Temperature (Cel)	260	Power Supplies	1.5/3.3 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Screening Level	AEC-Q100	Seated Height-Max	1.2 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.425 V
Supply Voltage-Nom	1.5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	AUTOMOTIVE
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	14 mm