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A3P600-FGG484 +BOM

A3P600-FGG484 Field Programmable Gate Array

Manufacturer:

Microchip Technology
Mfr.Part #:

A3P600-FGG484
Datasheet:

A3P600-FGG484 Datasheet (PDF)
Series:

ProASIC3
Programmabe:

Not Verified
Total RAM Bits:

110592
Number Of I/O:

235
EDA/CAD Models:

Request Free CAD Models for A3P600-FGG484

A3P600-FGG484 General Description

Microchip Technology's A3P600-FGG484 FPGA is a standout choice for engineers and designers seeking a powerful yet versatile solution for their application needs. With a formidable 600,000 system gates, this FPGA offers ample capacity for complex logic configurations. What sets it apart is its innovative Flash*Freeze technology, which delivers exceptionally low static power consumption, making it an environmentally friendly option that also contributes to cost savings. The device's reprogrammable flash technology allows for in-system programming, enabling flexibility and adaptability in various scenarios. Equipped with 293 user I/Os, the A3P600-FGG484 provides extensive connectivity options, while its support for high-speed interfaces like SPI, I2C, and UART ensures seamless integration into diverse systems. Additionally, the FPGA's security features, including non-volatile key storage and anti-tamper capabilities, make it an ideal choice for applications that demand robust data protection. Whether it's in the communications, industrial, or automotive sectors, the A3P600-FGG484 stands as a reliable and cost-effective solution for designs requiring moderate logic capacity and programmability, setting a new standard for versatility and performance

Key Features

High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced
Encryption Standard (AES) Decryption (except ARM®-
enabled ProASIC®3 devices) via JTAG (IEEE 1532–
compliant)†
FlashLock® to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os‡
Programmable Output Slew Rate† and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 and M7 ProASIC3 Devices—Cortex-M1 and
CoreMP7 Soft Processor Available with or without

Specifications

Series	ProASIC3	Programmabe	Not Verified
Total RAM Bits	110592	Number of I/O	235
Number of Gates	600000	Voltage - Supply	1.425V ~ 1.575V
Mounting Type	Surface Mount	Operating Temperature	0°C ~ 85°C (TJ)
Base Product Number	A3P600