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See Technical Specifications

A40MX04-PQG100 +BOM

MX Field Programmable Gate Array (FPGA) IC 69 100-BQFP

MX Field Programmable Gate Array (FPGA) IC 69 100-BQFP

High Capacity
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
High Performance
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG)Boundary Scan Testing

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Factory Lead Time	38 Weeks
Additional Feature	ALSO OPERATES AT 5V SUPPLY	Clock Frequency-Max	80 MHz
Combinatorial Delay of a CLB-Max	2.7 ns	JESD-30 Code	R-PQFP-G100
JESD-609 Code	e3	Length	20 mm
Moisture Sensitivity Level	3	Number of CLBs	547
Number of Equivalent Gates	6000	Number of Terminals	100
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	547 CLBS, 6000 GATES	Peak Reflow Temperature (Cel)	245
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	3.4 mm	Supply Voltage-Max	3.6 V
Supply Voltage-Min	3 V	Supply Voltage-Nom	3.3 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Finish	MATTE TIN
Terminal Form	GULL WING	Terminal Pitch	0.65 mm
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	30
Width	14 mm