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EP2S90F1020C5N is a Field Programmable Gate Array FPGA with 4548 LABs and 758 IOs, part of the Stratix II series
FBGA1020Manufacturer:
Mfr.Part #:
EP2S90F1020C5N
Datasheet:
Feature-family-name:
Stratix® II
Feature-process-technology:
90nm
Feature-maximum-number-of-user-i-os:
758
Feature-device-logic-cells:
90960
EDA/CAD Models:
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As part of the Stratix II family, the EP2S90F1020C5N is renowned for its reliability and scalability in digital design projects. Whether implementing complex algorithms or high-speed interfaces, this FPGA chip offers the resources and performance needed to bring innovative ideas to life. Its robust design and feature-rich capabilities make it a top choice for engineers and developers looking to push the boundaries of digital design
feature-family-name | Stratix® II | feature-process-technology | 90nm |
feature-maximum-number-of-user-i-os | 758 | feature-number-of-registers | |
feature-device-logic-cells | 90960 | feature-device-system-gates | |
feature-number-of-multipliers | 192 (18x18) | feature-program-memory-type | SRAM |
feature-ram-bits-kbit | 4414.5 | feature-total-number-of-block-ram | 4+408+488 |
feature-ethernet-macs | feature-supported-ip-core | Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz | |
feature-supported-ip-core-manufacture | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA | feature-maximum-number-of-serdes-channels | |
feature-device-logic-units | 90960 | feature-device-number-of-dlls-plls | 12 |
feature-transceiver-blocks | feature-transceiver-speed-gbps | ||
feature-dedicated-dsp | 48 | feature-pci-blocks | |
feature-programmability | No | feature-maximum-internal-frequency-mhz | 609.76 |
feature-speed-grade | 5 | feature-giga-multiply-accumulates-per-second | 50.4 |
feature-differential-i-o-standards-supported | LVPECL|LVDS | feature-single-ended-i-o-standards-supported | LVTTL|CMOS|SSTL|HSTL |
feature-external-memory-interface | DDR SDRAM|DDR2 SDRAM|RLDRAM II|QDRII+SRAM | feature-minimum-operating-supply-voltage-v | 1.15 |
feature-maximum-operating-supply-voltage-v | 1.25 | feature-packaging | |
feature-rad-hard | feature-pin-count | 1020 | |
feature-cecc-qualified | No | feature-esd-protection | |
feature-escc-qualified | feature-military | No | |
feature-aec-qualified | No | feature-aec-qualified-number | |
feature-auto-motive | No | feature-p-pap | No |
feature-eccn-code | 3A001.a.7.a | feature-svhc | Yes |
feature-svhc-exceeds-threshold | Yes |
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AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.
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Qty. | Unit Price | Ext. Price |
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The prices below are for reference only.
All bill of materials (BOM) can be sent via email to
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Corresponds to the description. Packaging is very reliable. delivery is very fast (very surprised).