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GAL16V8C-7LP +BOM

This SPLD GAL device features a total of 8 macro cells and comes in a 20-pin PDIP package

GAL16V8C-7LP General Description

The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speedperformance available in the PLD market. High speed erase times(<100ms) allow the devices to be reprogrammed quickly and efficiently.

The generic architecture provides maximum design flexibility byallowing the Output Logic Macrocell (OLMC) to be configured bythe user. An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listedin the table of the macrocell description section. GAL16V8 devicesare capable of emulating any of these PAL architectures with fullfunction/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,DC, and functional testing during manufacture. As a result, LatticeSemiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles anddata retention in excess of 20 years are specified.

gal16v8c-7lp gal16v8c-7lp

Specifications

Product Category SPLD - Simple Programmable Logic Devices Number of Macrocells 8
Maximum Operating Frequency 100 MHz Propagation Delay - Max 7.5 ns
Operating Supply Voltage 5 V Minimum Operating Temperature 0 C
Maximum Operating Temperature + 75 C Mounting Style Through Hole
Height 3.3 mm Length 26.16 mm
Moisture Sensitive Yes Operating Supply Current 115 mA
Product Type SPLD - Simple Programmable Logic Devices Series GAL16V8C
Factory Pack Quantity 18 Subcategory Programmable Logic ICs
Supply Voltage - Max 5.25 V Supply Voltage - Min 4.75 V
Width 6.35 mm Unit Weight 0.079719 oz

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T
T**x 09/18/2022

Quick quotes, fast shipping. Pallas is a safe bet.

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