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H5TQ2G63FFR-RDC +BOM

RESET DDR DRAM, 128MX16, 0.195ns, CMOS, PBGA96

Manufacturer:

SK HYNIX INC
Mfr.Part #:

H5TQ2G63FFR-RDC
Datasheet:

H5TQ2G63FFR-RDC Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

96
Reach Compliance Code:

compliant
ECCN Code:

EAR99

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

H5TQ2G63FFR-RDC General Description

The H5TQ2G43CFR-xxC, H5TQ2G83CFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Key Features

VDD=VDDQ=1.5V +/- 0.075V

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

On chip DLL align DQ, DQS and DQS transition with CK

transition

DM masks write data-in at the both rising and falling

edges of the data strobe

All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13

and 14 supported

Programmable additive latency 0, CL-1, and CL-2

supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10

Programmable burst length 4/8 with both nibble

sequential and interleave mode

BL switch on the fly

8banks

Average Refresh Cycle (Tcase of0 oC~ 95oC)

- 7.8 s at 0oC ~ 85 oC

- 3.9 s at 85oC ~ 95 oC

JEDEC standard 78ball FBGA(x4/x8)

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

ZQ calibration supported

TDQS (Termination Data Strobe) supported (x8 only)

Write Levelization supported

8 bit pre-fetch

This product in compliance with the RoHS directive.

Specifications

Part Life Cycle Code	Obsolete	Pin Count	96
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.36	Access Mode	MULTI BANK PAGE BURST
Access Time-Max	0.195 ns	Additional Feature	AUTO/SELF REFRESH
Clock Frequency-Max (fCLK)	933 MHz	I/O Type	COMMON
Interleaved Burst Length	4,8	JESD-30 Code	R-PBGA-B96
Length	13 mm	Memory Density	2147483648 bit
Memory IC Type	DDR3 DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	96	Number of Words	134217728 words
Number of Words Code	128000000	Operating Mode	SYNCHRONOUS
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	128MX16	Output Characteristics	3-STATE
Peak Reflow Temperature (Cel)	NOT SPECIFIED	Power Supplies	1.5 V
Qualification Status	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	4,8	Standby Current-Max	0.012 A
Supply Current-Max	0.22 mA	Supply Voltage-Max (Vsup)	1.575 V
Supply Voltage-Min (Vsup)	1.425 V	Supply Voltage-Nom (Vsup)	1.5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	OTHER	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED	Width	7.5 mm