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KSZ9031MNXIA +BOM
KSZ9031MNXIA - Single-Port Ethernet Transceiver Supporting 10/100/1000 Mbps Speeds, Encased in a 64-Pin QFN EP Package
QFN-64-
Manufacturer:
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Mfr.Part #:
KSZ9031MNXIA
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Datasheet:
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Part Life Cycle Code:
Active
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Reach Compliance Code:
compliant
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ECCN Code:
EAR99
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HTS Code:
8517.70.00.00
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EDA/CAD Models:
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Availability: 5252 PCS
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KSZ9031MNXIA General Description
The KSZ9031MNXIA Ethernet transceiver is a versatile and efficient networking solution for high-performance applications. Its low-power consumption mode ensures energy efficiency, while its auto-negotiation and automatic polarity correction capabilities make network setup a breeze. With support for IEEE standards and various interfaces, this transceiver is compatible with a wide range of devices, enabling seamless integration into existing systems
Key Features
- Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver
- GMII/MII standard interface with 3.3V/2.5V/1.8V tolerant I/Os
- Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
- On-chip termination resistors for the differential pairs
- On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
- Jumbo frame support up to 16KB
- 125MHz reference clock output
- Energy-detect power-down mode for reduced power consumption when the cable is not attached
- Energy Efficient Ethernet (EEE) support with low-power idle (LPI) mode and clock stoppage for 100Base-TX/1000Base-T and transmit amplitude reduction with 10Base-Te option
- Wake-on-LAN (WOL) support with robust custom-packet detection
- Programmable LED outputs for link, activity, and speed
- Baseline wander correction
- LinkMD TDR-based cable diagnostic to identify faulty copper cabling
- Parametric NAND tree support to detect faults between chip I/Os and board.
- Loopback modes for diagnostics
- Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation
- Automatic detection and correction of pair swaps, pair skew, and pair polarity
- MDC/MDIO management interface for PHY register configuration
- Interrupt pin option
- Power-down and power-saving modes
- Operating voltages
- – Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator)
- – VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
- – Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
- Available in a 64-pin QFN (8mm x 8mm) package
Specifications
Source Content uid | KSZ9031MNXIA | Part Life Cycle Code | Active |
Reach Compliance Code | compliant | ECCN Code | EAR99 |
HTS Code | 8517.70.00.00 | Date Of Intro | 2016-02-19 |
Data Rate | 1000000 Mbps | JESD-30 Code | S-XQCC-N64 |
JESD-609 Code | e3 | Length | 8 mm |
Number of Functions | 1 | Number of Terminals | 64 |
Number of Transceivers | 1 | Operating Temperature-Max | 85 °C |
Operating Temperature-Min | -40 °C | Peak Reflow Temperature (Cel) | 260 |
Seated Height-Max | 0.9 mm | Supply Voltage-Nom | 1.2 V |
Surface Mount | YES | Telecom IC Type | ETHERNET TRANSCEIVER |
Temperature Grade | INDUSTRIAL | Terminal Finish | MATTE TIN |
Terminal Form | NO LEAD | Terminal Pitch | 0.4 mm |
Terminal Position | QUAD | Time@Peak Reflow Temperature-Max (s) | 30 |
Width | 8 mm |
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In Stock: 5,252
Minimum Order: 1
Qty. | Unit Price | Ext. Price |
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1+ | - | - |
The prices below are for reference only.
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