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LCMXO1200C-3TN100I +BOM

1200 LUT FPGA with 73 I/O connections, designed for industrial use and compatible with multiple voltage levels

Manufacturer:

LATTICE SEMICONDUCTOR CORP
Mfr.Part #:

LCMXO1200C-3TN100I
Datasheet:

LCMXO1200C-3TN100I Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

100
Reach Compliance Code:

compliant
EDA/CAD Models:

Request Free CAD Models for LCMXO1200C-3TN100I

LCMXO1200C-3TN100I General Description

LCMXO1200C-3TN100I, a member of the Lattice XO2-1200 family, stands out as a low-cost, low-power FPGA with impressive capabilities. Its 1200 Look-Up Tables (LUTs) allow for the implementation of complex logic functions, while its -3 speed grade ensures support for clock frequencies up to 300 MHz. The device's 149 I/O pins and compact 100-pin TQFP package make it suitable for applications where space is limited. With a typical static power consumption of only 19 mW, LCMXO1200C-3TN100I is an ideal choice for power-sensitive designs. Furthermore, its on-chip programming capabilities and support for various I/O standards such as LVCMOS, LVTTL, and LVDS enhance its versatility and compatibility with different interface protocols

Key Features

Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single chip, no external configuration memory
required
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
Sleep Mode
Allows up to 100x static current reduction
TransFR™ Reconfiguration (TFR)
In-field logic update while system operates
High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
Flexible I/O Buffer
Programmable sysIO™ buffer supports wide
range of interfaces:
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK™ PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming

LATTICE SEMICONDUCTOR CORP Original Stock

Specifications

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	100	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
JESD-30 Code	S-PQFP-G100	JESD-609 Code	e3
Length	14 mm	Moisture Sensitivity Level	3
Number of CLBs	150	Number of Inputs	73
Number of Logic Cells	1200	Number of Outputs	73
Number of Terminals	100	Operating Temperature-Max	100 °C
Operating Temperature-Min	-40 °C	Organization	150 CLBS
Peak Reflow Temperature (Cel)	260	Power Supplies	1.8/3.3 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	1.71 V	Supply Voltage-Nom	1.8 V
Surface Mount	YES	Temperature Grade	INDUSTRIAL
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	40	Width	14 mm
Series	MachXO	Programmabe	Not Verified
Number of LABs/CLBs	150	Number of Logic Elements/Cells	1200
Total RAM Bits	9421	Number of I/O	73
Voltage - Supply	1.71V ~ 3.465V	Mounting Type	Surface Mount
Operating Temperature	-40°C ~ 100°C (TJ)	Base Product Number	LCMXO1200