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Dual loop PLLs clock jitter cleaner with ultra low-noise
WQFN-64Manufacturer:
Mfr.Part #:
LMK04228NKDT
Datasheet:
Function:
Dual-loop PLL
Number Of Outputs:
15
RMS Jitter (fs):
156
Output Frequency (min) (MHz):
0.315
EDA/CAD Models:
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Incorporating cutting-edge features such as power-performance trade-offs, dual VCOs, holdover capabilities, and adjustable analog and digital delay per output, the LMK04228NKDT offers unparalleled flexibility in building high-performance clocking structures. Whether you are working with JESD204B applications or looking to optimize clocking systems, this device provides the perfect balance of flexibility and performance to meet your specific requirements. Its industry-leading performance and versatility make it the go-to choice for creating robust clocking trees that can adapt to your evolving needs
Function | Dual-loop PLL | Number of outputs | 15 |
RMS jitter (fs) | 156 | Output frequency (min) (MHz) | 0.315 |
Output frequency (max) (MHz) | 1250 | Input type | LVCMOS, LVDS, LVPECL |
Output type | LVCMOS, LVDS, LVPECL | Supply voltage (min) (V) | 3.15 |
Supply voltage (max) (V) | 3.45 | Features | JESD204B |
Rating | Catalog | Operating temperature range (°C) | -40 to 85 |
Number of input channels | 3 | feature-maximum-operating-supply-voltage-v | 3.45 |
feature-minimum-operating-supply-voltage-v | 3.15 | feature-packaging | Tape and Reel |
feature-rad-hard | feature-pin-count | 64 | |
feature-cecc-qualified | feature-esd-protection | ||
feature-escc-qualified | feature-military | No | |
feature-aec-qualified | No | feature-aec-qualified-number | |
feature-auto-motive | No | feature-p-pap | No |
feature-eccn-code | EAR99 | feature-svhc | |
feature-svhc-exceeds-threshold | No |
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AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.
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