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MB91F313A +BOM

Key Features

  • 1. FR CPU
  • 32-bit RISC load/store architecture with a five-stage pipeline
  • Operating frequency 33 MHz (oscillator frequency: 16.5 MHz; oscillator frequency multiplier: 2 (PLL clock
  • multiplication method))
  • 16-bit fixed length instructions (basic instructions)
  • Instruction execution speed : 1 instruction per cycle
  • Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions : Instructions suitable for embedded applications
  • Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C language
  • Register interlock functions : Facilitates assembly-language coding
  • On-chip multiplier supported at the instruction level
  • - Signed 32-bit multiplication : 5 cycles
  • - Signed 16-bit multiplication : 3 cycles
  • Interrupt (PC, PS save) : 6 cycles, 16 priority levels
  • Harvard architecture enabling program access and data access to be executed simultaneously
  • Instruction prefetch feature implemented using a 4-word queue in the CPU
  • Instruction compatible with the FR family

Specifications

Product Category IC Chips

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In Stock: 7,072

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