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See Technical Specifications

MC68HC912B32 +BOM

MicroController, 16-Bit, 80 Pin, Plastic, QFP

Manufacturer:

FREESCALE
Mfr.Part #:

MC68HC912B32
Datasheet:

MC68HC912B32 Datasheet (PDF)
Package/Case:

QFP80
RoHS:
EDA/CAD Models:

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MC68HC912B32 General Description

The MC68HC912B32 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 32-Kbyte flash EEPROM, 1-Kbyte RAM, 768-byte EEPROM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel timer and 16-bit pulse accumulator, an 8-bit analog-to-digital converter (ADC), a four-channel pulse-width modulator (PWM), and a J1850-compatible byte data link communications module (BDLC). The chip is the first 16-bit microcontroller to include both byte-erasable EEPROM and flash EEPROM on the same device. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the Lite integration module (LIM). The MC68HC912B32 has full 16-bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems.Features• 16-Bit CPU12— Upward Compatible with M68HC11 Instruction Set— Interrupt Stacking and Programmer’s Model Identical to M68HC11— 20-Bit ALU— Instruction Queue— Enhanced Indexed Addressing— Fuzzy Logic Instructions• Multiplexed Bus— Single Chip or Expanded— 16/16 Wide or 16/8 Narrow Modes• Memory— 32-Kbyte Flash EEPROM with 2-Kbyte Erase-Protected Boot Block— 768-B yte EEPROM— 1-Kbyte RAM with Single-Cycle Access for Aligned or Misaligned Read/Write• 8-Channel, 8-Bit Analog-to-Digital Converter• 8-Channel Timer— Each Channel Fully Configurable as Either Input Capture or Output Compare— Simple PWM Mode— Modulo Reset of Timer Counter• 16-Bit Pulse Accumulator— External Event Counting— Gated Time Accumulation• Pulse-Width Modulator— 8-Bit, 4-Channel or 16-Bit, 2-Channel— Separate Control for Each Pulse Width and Duty Cycle

Key Features

Features include:
16-bit CPU12:
– Upwardly compatible with the M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to the M68HC11
– 20-bit arithmetic logic unit (ALU)
– Instruction queue
– Enhanced indexed addressing
– Fuzzy logic instructions
Multiplexed bus:
– Single chip or expanded
– 16-bit by 16-bit wide or 16-bit by 8-bit narrow modes
Memory:
– 32-Kbyte FLASH electrically erasable, programmable read-only memory (EEPROM) with 2-Kbyte erase-protected boot block — MC68HC912B32 and MC68HC912BC32 only
– 32-Kbyte ROM — MC68HC12BE32 and MC68HC12BC32 only
– 768-byte EEPROM
– 1-Kbyte random-access memory (RAM) with single-cycle access for aligned or misaligned read/write
8-channel, 10-bit analog-to-digital converter (ATD)
8-channel standard timer module (TIM) — MC68HC912B32 and MC68HC(9)12BC32 only:
– Each channel fully configurable as either input capture or output compare
– Simple pulse-width modulator (PWM) mode
– Modulus reset of timer counter
Enhanced capture timer (ECT) — MC68HC12BE32 only:
– 16-bit main counter with 7-bit prescaler
– Eight programmable input capture or output compare channels; four of the eight input captures with buffer
– Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators
– 16-bit modulus down-counter with 4-bit prescaler
– Four user-selectable delay counters for signal filtering
16-bit pulse accumulator:
– External event counting
– Gated time accumulation
Pulse-width modulator (PWM):
– 8-bit, 4-channel or 16-bit, 2-channel
– Separate control for each pulse width and duty cycle
– Programmable center-aligned or left-aligned outputs
Serial interfaces:
– Asynchronous serial communications interface (SCI)
– Synchronous serial peripheral interface (SPI)
– J1850 byte data link communication (BDLC), MC68HC912B32 and MC68HC12BE32 only
– Controller area network (CAN), MC68HC(9)12BC32 only
Computer operating properly (COP) watchdog timer, clock monitor, and periodic interrupt timer
Slow-mode clock divider
80-pin quad flat pack (QFP)
Up to 63 general-purpose input/output (I/O) lines
Single-wire background debug mode (BDM)
On-chip hardware breakpoints