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MT47H128M16HG-3IT +BOM

High-Speed DRAM for Efficient Computi

MT47H128M16HG-3IT

Key Features

  • VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V
  • JEDEC-standard 1.8V I/O (SSTL_18-compatible)
  • Differential data strobe (DQS, DQS#) option
  • 4n-bit prefetch architecture
  • Duplicate output strobe (RDQS) option for x8
  • DLL to align DQ and DQS transitions with CK
  • 8 internal banks for concurrent operation
  • Programmable CAS latency (CL)
  • Posted CAS additive latency (AL)
  • WRITE latency = READ latency - 1 tCK
  • Selectable burst lengths (BL): 4 or 8
  • Adjustable data-output drive strength
  • 64ms, 8192-cycle refresh
  • On-die termination (ODT)
  • Industrial temperature (IT) option
  • Automotive temperature (AT) option
  • RoHS-compliant
  • Supports JEDEC clock jitter specification

Specifications

Part Life Cycle Code Active Reach Compliance Code compliant
ECCN Code EAR99 HTS Code 8542.32.00.36
Access Mode MULTI BANK PAGE BURST Access Time-Max 0.45 ns
Additional Feature AUTO/SELF REFRESH JESD-30 Code R-PBGA-B84
Length 14 mm Memory Density 2147483648 bit
Memory IC Type DDR2 DRAM Memory Width 16
Number of Functions 1 Number of Ports 1
Number of Terminals 84 Number of Words 134217728 words
Number of Words Code 128000000 Operating Mode SYNCHRONOUS
Operating Temperature-Max 85 °C Operating Temperature-Min -40 °C
Organization 128MX16 Seated Height-Max 1.2 mm
Self Refresh YES Supply Voltage-Max (Vsup) 1.9 V
Supply Voltage-Min (Vsup) 1.7 V Supply Voltage-Nom (Vsup) 1.8 V
Surface Mount YES Technology CMOS
Temperature Grade INDUSTRIAL Terminal Form BALL
Terminal Pitch 0.8 mm Terminal Position BOTTOM
Width 11.5 mm

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