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PKD01EY +BOM

Sample and Hold 2-CH 70us 14-Pin CDIP

pkd01ey pkd01ey

Key Features


Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/μs
Low Droop Rate
TA = 25°C: 0.1 mV/ms
TA = 125°C: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form

Specifications

place Philippines launch_date Feb 28, 2001
last_inspection_date 07 APR 2023 supplier_cage_code 24355
htsusa 8542390001 schedule_b 8542390000
ppap False aec False

Service Policies and Others

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Packing

AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.

Warranty Warranty

We promise to provide 365 days quality assurance service for all our products.

Ratings and Reviews

More
D
D**n 02/22/2020

Perfect shipping, very fast.

16

Reviews

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In Stock: 4,676

Minimum Order: 1

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