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See Technical Specifications

PUMH20 +BOM

NXP Semiconductors

Manufacturer:

NXP
Mfr.Part #:

PUMH20
Datasheet:

PUMH20 Datasheet (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
Date Of Intro:

2017-02-01

PUMH20 General Description

NPN/NPN double Resistor-Equipped Transistor (RET) in a very small SOT363 (SC-88) Surface-Mounted Device (SMD) plastic package.NPN/PNP complement: PUMD20PNP/PNP complement: PUMB20

Key Features

Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified

Application

Low current peripheral driver
Control of IC inputs
Replacement of general-purpose transistors in digital applications

Specifications

Source Content uid	PUMH20	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	EAR99
Date Of Intro	2017-02-01	Additional Feature	BUILT IN BIAS RESISTOR RATIO IS 1
Collector Current-Max (IC)	0.1 A	Collector-Base Capacitance-Max	2.5 pF
Collector-Emitter Voltage-Max	50 V	Configuration	SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
DC Current Gain-Min (hFE)	30	JESD-30 Code	R-PDSO-G6
JESD-609 Code	e3	Moisture Sensitivity Level	1
Number of Elements	2	Number of Terminals	6
Operating Temperature-Max	150 °C	Operating Temperature-Min	-65 °C
Peak Reflow Temperature (Cel)	260	Polarity/Channel Type	NPN
Power Dissipation-Max (Abs)	0.3 W	Reference Standard	AEC-Q101; IEC-60134
Surface Mount	YES	Terminal Finish	TIN
Terminal Form	GULL WING	Terminal Position	DUAL
Time@Peak Reflow Temperature-Max (s)	30	Transistor Application	SWITCHING
Transistor Element Material	SILICON	VCEsat-Max	0.15 V