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See Technical Specifications

TDA8007B +BOM

Smart Card Interface 10MHz 3.3V/5V 700mW 48-Pin LQFP

Manufacturer:

NXP Semiconductor
Mfr.Part #:

TDA8007B
Datasheet:

TDA8007B Datasheet (PDF)
Place:

China
Launch_date:

Nov 11, 1999
Last_inspection_date:

03 MAY 2023
Supplier_cage_code:

H1R01
EDA/CAD Models:

Request Free CAD Models for TDA8007B

Key Features

• Control and communication through an 8-bit parallel interface, compatible with multiplexed or non-multiplexed memory access
• Specific ISO UART with parallel access on I/O for automatic convention processing, variable baud rate through frequency or division ratio programming, error management at character level for T = 0, extra guard time register
• 1 to 8 characters FIFO in reception mode
• Parity error counter in reception mode
• Dual VCC generation (5 V ±5%, 65 mA (max.) or 3 V ±8%, 50 mA (max.) with controlled rise and fall times)
• Dual cards clock generation (up to 10 MHz), with two times synchronous frequency doubling
• Cards clock STOP HIGH, clock STOP LOW or 1.25 MHz (from internal oscillator) for cards Power-down mode
• Automatic activation and deactivation sequence through an independent sequencer
• Supports the asynchronous protocols T = 0 and T = 1 in accordance with ISO 7816 and EMV
• Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times processing
• 22 Elementary Time Unit (ETU) counter for Block Guard Time (BGT)
• Supports synchronous cards
• Current limitations in the event of short-circuit
• Special circuitry for killing spikes during power-on/-off
• Supply supervisor for power-on/-off reset
• Step-up converter (supply voltage from 2.7 to 6 V), doubler, tripler or follower according to VCC and VDD
• Additional I/O pin allowing use of the ISO UART for another analog interface (pin I/OAUX)
• Additional interrupt pin allowing detection of level toggling on an external signal (pin INTAUX)
• Fast and efficient swapping between the 3 cards due to separate buffering of parameters for each card
• Chip select input allowing use of several devices in parallel and memory space paging
• Enhanced ESD protections on card side [6 kV (min.)]
• Software library for easy integration within the application
• Power-down mode for reducing current consumption when no activity.

Specifications

place	China	launch_date	Nov 11, 1999
last_inspection_date	03 MAY 2023	supplier_cage_code	H1R01
htsusa	8542390001	schedule_b	8542390000
ppap	False	aec	False

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Packing

AVAQ determines and packages all devices based on electrostatic discharge (ESD) and moisture sensitivity level (MSL) protection requirements.

Warranty

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Ratings and Reviews

M**r 08/04/2023

The order came quite quickly, everything is safe and sound. The product is made qualitatively, the soldering is ideal, the flux is washed, the equipment is such as ordered, the packaging is a standard dense envelope and an antistatic package. Seller advise!!!

M**l 03/03/2023

not yet tested , looks good !

A**n 02/25/2022

Cheap GPS with smal antenna .... not teste yet, but cheap it was ;)

T**r 10/25/2021

Fast shipping nicer.