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See Technical Specifications

UPD48576118F1-E18-DW1-A +BOM

576M-BIT Low Latency DRAM Separate I/O

Manufacturer:

Renesas
Mfr.Part #:

UPD48576118F1-E18-DW1-A
Datasheet:

UPD48576118F1-E18-DW1-A Datasheet (PDF)
Programmabe:

Not Verified
Memory Type:

Volatile
Memory Format:

DRAM
Technology:

LLDRAM
EDA/CAD Models:

Request Free CAD Models for UPD48576118F1-E18-DW1-A

UPD48576118F1-E18-DW1-A General Description

The µPD48576118F1 is a 33, 554, 432 word by 18 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The µPD48576118F1 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration.

Key Features

SRAM-type interface
Double-data-rate architecture
PLL circuitry
Cycle time: 1.875 ns @ t_RC = 15 ns 2.5 ns @ t_RC = 15 ns 2.5 ns @ t_RC = 20 ns 3.3 ns @ t_RC = 20 ns
Non-multiplexed addresses
Multiplexing option is available.
Data mask for WRITE commands
Differential input clocks (CK and CK#)
Differential input data clocks (DK and DK#)
Data valid signal (QVLD)
Programmable burst length: 2 / 4 / 8 (x18)
User programmable impedance output (25 Ω - 60 Ω)
JTAG boundary scan

Specifications

Series	-	Programmabe	Not Verified
Memory Type	Volatile	Memory Format	DRAM
Technology	LLDRAM	Memory Size	576Mbit
Memory Organization	32M x 18	Memory Interface	HSTL
Clock Frequency	533 MHz	Write Cycle Time - Word, Page	-
Access Time	300 ps	Voltage - Supply	1.7V ~ 1.9V
Operating Temperature	0°C ~ 95°C (TC)	Mounting Type	Surface Mount
Base Product Number	UPD48576118