This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

XC2V1000-5FGG256I +BOM

free PBGA256 package with 1mm pitch

Manufacturer:

XILINX
Mfr.Part #:

XC2V1000-5FGG256I
Datasheet:

XC2V1000-5FGG256I Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Obsolete
Pin Count:

256
ECCN Code:

EAR99
EDA/CAD Models:

Request Free CAD Models for XC2V1000-5FGG256I

XC2V1000-5FGG256I General Description

The XC2V1000-5FGG256I by Xilinx stands out as a versatile FPGA within the Virtex-II family, boasting a robust capacity of 1,000,000 system gates. This FPGA operates at a speed grade of -5, ensuring optimal performance for intricate digital designs. Housed in a 256-ball FBGA package, it offers compact integration onto circuit boards without compromising on functionality. With a myriad of I/O pins, this FPGA facilitates seamless interfacing with external devices and systems, making it a reliable choice for diverse applications

Specifications

Pbfree Code	Yes	Part Life Cycle Code	Obsolete
Pin Count	256	Reach Compliance Code
ECCN Code	EAR99	HTS Code	8542.39.00.01
Clock Frequency-Max	750 MHz	Combinatorial Delay of a CLB-Max	0.39 ns
JESD-30 Code	S-PBGA-B256	JESD-609 Code	e1
Length	17 mm	Moisture Sensitivity Level	3
Number of CLBs	1280	Number of Equivalent Gates	1000000
Number of Inputs	172	Number of Logic Cells	11520
Number of Outputs	172	Number of Terminals	256
Organization	1280 CLBS, 1000000 GATES	Peak Reflow Temperature (Cel)	260
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	2 mm	Supply Voltage-Max	1.575 V
Supply Voltage-Min	1.425 V	Supply Voltage-Nom	1.5 V
Surface Mount	YES	Technology	CMOS
Terminal Finish	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	30	Width	17 mm