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See Technical Specifications

XC2VP40-5FF1152C +BOM

FPGA Virtex-II Pro Family with 43632 cells and 1050MHz

Manufacturer:

XILINX
Mfr.Part #:

XC2VP40-5FF1152C
Datasheet:

XC2VP40-5FF1152C Datasheet (PDF)
Pbfree Code:

No
Part Life Cycle Code:

Obsolete
Pin Count:

1152
Reach Compliance Code:

not_compliant
EDA/CAD Models:

Request Free CAD Models for XC2VP40-5FF1152C

XC2VP40-5FF1152C General Description

Featuring 1152 Inputs/Outputs with a FineLine BGA package, the XC2VP40-5FF1152C is versatile when it comes to interfacing with other components. It operates on a core voltage of 1.2 V and supports various I/O standards such as LVDS, LVTTL, and HSTL. In addition, it comes equipped with built-in DCMs for managing clock signals, providing flexibility in clocking options. With support for up to 800 MHz of internal logic performance, this FPGA is well-suited for applications requiring high-speed processing

Specifications

Pbfree Code	No	Part Life Cycle Code	Obsolete
Pin Count	1152	Reach Compliance Code	not_compliant
ECCN Code	3A991.D	HTS Code	8542.39.00.01
Clock Frequency-Max	1050 MHz	Combinatorial Delay of a CLB-Max	0.36 ns
JESD-30 Code	S-PBGA-B1152	JESD-609 Code	e0
Length	35 mm	Moisture Sensitivity Level	4
Number of CLBs	4848	Number of Inputs	692
Number of Logic Cells	43632	Number of Outputs	644
Number of Terminals	1152	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	4848 CLBS
Peak Reflow Temperature (Cel)	225	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	3.4 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.425 V
Supply Voltage-Nom	1.5 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	Tin/Lead (Sn63Pb37)	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	30	Width	35 mm