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128M X 16 DDR DRAM PBGA96
FBGA96Manufacturer:
SKHYNIX
Mfr.Part #:
H5TQ2G63FFR-PBC
Datasheet:
Package/Case:
FBGA96
Product Type:
EDA/CAD Models:
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VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK
transition
DM masks write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
Programmable additive latency 0, CL-1, and CL-2
supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
Programmable burst length 4/8 with both nibble
sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of0 oC~ 95oC)
- 7.8 s at 0oC ~ 85 oC
- 3.9 s at 85oC ~ 95 oC
JEDEC standard 78ball FBGA(x4/x8)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
This product in compliance with the RoHS directive.
Product Category | Memory ICs |
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