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Quad D-type flip-flop
16-SOManufacturer:
Mfr.Part #:
HEF40175BT,653
Datasheet:
Feature-logic-family:
HEF4000
Feature-logic-function:
D-Type Bus Interface
Feature-number-of-elements-per-chip:
1
Feature-process-technology:
CMOS
EDA/CAD Models:
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The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset () inputs, and complementary Qn and n outputs. When is HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW, resets all flip-flops (Qn = LOW, n = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V.
feature-logic-family | HEF4000 | feature-logic-function | D-Type Bus Interface |
feature-number-of-elements-per-chip | 1 | feature-process-technology | CMOS |
feature-maximum-operating-supply-voltage-v | 15 | feature-maximum-high-level-output-current-ma | -4.2 |
feature-output-type | feature-maximum-low-level-output-current-ma | 4.2(Min) | |
feature-packaging | Tape and Reel | feature-minimum-operating-supply-voltage-v | 3 |
feature-rad-hard | feature-pin-count | 16 | |
feature-cecc-qualified | No | feature-esd-protection | |
feature-military | No | feature-aec-qualified | No |
feature-aec-qualified-number | feature-auto-motive | No | |
feature-p-pap | No | feature-eccn-code | EAR99 |
feature-svhc | No | feature-svhc-exceeds-threshold | No |
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