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See Technical Specifications

HEF4021BT,653 +BOM

8-bit static shift register

Manufacturer:

Nexperia Semiconductor (NXP)
Mfr.Part #:

HEF4021BT,653
Datasheet:

HEF4021BT,653 Datasheet (PDF)
Feature-logic-family:

HEF4000
Feature-logic-function:

Shift Register
Feature-number-of-elements-per-chip:

1
Feature-process-technology:

CMOS
EDA/CAD Models:

Request Free CAD Models for HEF4021BT,653

HEF4021BT,653 General Description

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.The device operates over a recommended V power supply range of 3 V to 15 V referenced to V (usually ground). Unused inputs must be connected to V, V, or another input.

Key Features

Wide supply voltage range from 3.0 V to 15.0 V
CMOS low power dissipation
High noise immunity
Tolerant of slower rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Complies with JEDEC standard JESD 13-B
ESD protection:HBM JESD22-A114F exceeds 2000 VMM JESD22-A115-B exceeds 200 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Nexperia Semiconductor (NXP) Original Stock

Specifications

feature-logic-family	HEF4000	feature-logic-function	Shift Register
feature-number-of-elements-per-chip	1	feature-process-technology	CMOS
feature-maximum-low-level-output-current-ma		feature-output-type
feature-minimum-operating-supply-voltage-v	3	feature-maximum-operating-supply-voltage-v	15
feature-maximum-high-level-output-current-ma		feature-packaging	Tape and Reel
feature-rad-hard		feature-pin-count	16
feature-cecc-qualified	No	feature-esd-protection
feature-military	No	feature-aec-qualified	No
feature-aec-qualified-number		feature-auto-motive	No
feature-p-pap	No	feature-eccn-code	EAR99
feature-svhc	No	feature-svhc-exceeds-threshold	No