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K4H511638D-ZCB3 +BOM

DDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60

Key Features

VDD : 2.5V0.2V, VDDQ : 2.5V0.2V for DDR266, 333

VDD : 2.6V0.1V, VDDQ : 2.6V0.1V for DDR400

Double-data-rate architecture; two data transfers per clock cycle

Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)

Four banks operation

Differential clock inputs(CK and CK)

DLL aligns DQ and DQS transition with CK transition

MRS cycle with address key programs

-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

Data I/O transactions on both edges of data strobe

Edge aligned data output, center aligned data input

LDM,UDM for write masking only (x16)

DM for write masking only (x4, x8)

Auto & Self refresh

7.8us refresh interval(8K/64ms refresh)

Maximum burst refresh cycle : 8

66pin TSOP II Pb-Free package

RoHS compliant

Specifications

Pbfree Code Yes Part Life Cycle Code Obsolete
Reach Compliance Code compliant ECCN Code EAR99
HTS Code 8542.32.00.28 Access Time-Max 0.7 ns
Clock Frequency-Max (fCLK) 166 MHz I/O Type COMMON
Interleaved Burst Length 2,4,8 JESD-30 Code R-PBGA-B60
Memory Density 536870912 bit Memory IC Type DDR1 DRAM
Memory Width 16 Moisture Sensitivity Level 3
Number of Terminals 60 Number of Words 33554432 words
Number of Words Code 32000000 Operating Temperature-Max 70 °C
Operating Temperature-Min Organization 32MX16
Output Characteristics 3-STATE Peak Reflow Temperature (Cel) 260
Power Supplies 2.5 V Qualification Status Not Qualified
Refresh Cycles 8192 Sequential Burst Length 2,4,8
Standby Current-Max 0.005 A Supply Current-Max 0.38 mA
Supply Voltage-Nom (Vsup) 2.5 V Surface Mount YES
Technology CMOS Temperature Grade COMMERCIAL
Terminal Form BALL Terminal Pitch 0.8 mm
Terminal Position BOTTOM

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